Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

4.7.1. Enabling Interrupts

You can enable the ECC error or event counter overflow interrupts in the CCC by programming the CCC Interrupt Mask register (agent_ccc0_ccc_interrupt_mask) at offset 0x30190. You can track the interrupt status by reading the CCC Interrupt Status register (agent_ccc0_ccc_interrupt_err) at offset 0x30198.

You can enable read, write or counter overflow error interrupts in a specific bridge by programming the bridge's Interrupt Mask register (*am_intm*). You can track error status by reading the bridge's Status and Error register (*am_err*).