Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

6.2.5.1.3. HPS-to-FPGA Clock Domain

The HPS-to-FPGA domain is used purely by the HPS-to-FPGA bridge. The FPGA drives the HPS-to-FPGA clock, which is asynchronous to all other clocks.

Table 68.  Clocks in the HPS-to-FPGA Domain
Group Clock Enables Nominal Ratio Reset Usage
soc2fpga_clk soc2fgpa_bridge_rst_n