Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

8.3. Functional Description of the DMA Controller

This section describes the major interfaces and components of the DMAC and its operation.

The DMAC has eight DMA channels. Each channel supports a single concurrent thread of DMA operation. In addition, a single DMA manager thread exists, and you can use it to initialize the DMA channel threads.

For more information, refer to the CoreLink DMA-330 DMA Controller Technical Reference Manual on the Arm* Infocenter website.

The DMAC includes a 16-line instruction cache to improve the instruction fetch performance. Each instruction cache line contains eight, 4-byte words for a total cache line size of 32 bytes. The DMAC instruction cache size is, 16 lines times 32 bytes per line which equals 512 bytes. There is no mechanism to preload the program code into the DMA cache before the corresponding thread starts executing. The initial latency to bring the code into cache and start executing is dependent on where the code resides. This initial latency should be taken into consideration at system level to optimize the DMA transfers and expected performance. When a thread requests an instruction from an address, the cache performs a lookup. If a cache hit occurs, the cache immediately provides the instruction. Otherwise, the thread is stalled while the DMAC performs a cache line fill through the AXI master interface. If an instruction spans the end of a cache line, the DMAC performs multiple cache accesses to fetch the instruction.

Note: When a cache line fill is in progress, the DMAC enables other threads to access the cache. But if another cache fill occurs, the pipeline stalls until the first line fill is complete.

When a DMA channel thread executes a load or store instruction, the DMAC adds the instruction to the relevant read or write queue. The DMAC uses these queues as an instruction storage buffer prior to it issuing the instructions on the AXI bus. The DMAC also contains an MFIFO data buffer in which it stores data that it reads or writes during a DMA transfer.

The DMAC provides nine interrupt outputs to enable efficient communication of events to the system CPUs. The peripheral request interfaces support the connection of DMA–capable peripherals to enable memory–to–peripheral and peripheral–to–memory DMA transfers to occur without intervention from the microprocessor.

Dual slave interfaces enable the operation of the DMAC to be partitioned into the secure state and non–secure states. You can access status registers and also directly execute instructions in the DMAC with the slave interfaces.