Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

7.3.1.1. FPGA-to-SDRAM direct ( AXI* 4)

  • All operations bypass the CCU and are non-coherent.
  • For all burst transactions, AxBURST must be either ‘b01 (INCR) or ‘b10 (WRAP).