Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

3.5.14. Generic Timers

The Arm* Cortex* -A53 MPCore provides a generic timer within each CPU.

The generic timer of each CPU contains a set of timer registers to capture a variety of events:

  • non-secure physical events
  • secure physical events
  • physical events
  • virtual events

The four timers provided in each CPU are:

  • EL1 non-secure physical timer register
  • EL1 secure physical timer register
  • EL2 virtual physical timer register
  • Hypervisor timer register

You can configure the generic timers as count-up or count-down timers and they can operate in real-time and during virtual memory operation. You can also program a starting value for each generic timer.

Each of these timers has a 64‑bit comparator that generates a private interrupt when the counter reaches the specified value. These interrupts are sent as a private peripheral interrupt with separate PPI ID.

Table 37.  Private Peripheral Interrupt (PPI) ID Assignments
Timer PPI ID
EL1 non-secure physical timer 30
EL1 secure physical timer 29
EL2 virtual physical timer 27
Hypervisor timer 26

For more information about the generic timers, please refer to the Arm* Cortex* -A53 MPCore Processor Technical Reference Manual, and the Arm* Architecture Reference Manual ARMv8, for ARMv8-A Architecture.