Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

5.3. System Integration

The SMMU comprises the translation control unit (TCU) that interfaces to five distributed translation buffer units (TBUs).

The TBUs interface to the following masters:

  • FPGA
  • DMA
  • EMAC0-2, collectively
  • USB0-1, NAND controller, SD/MMC controller, Arm* Embedded Trace Router (ETR), collectively
  • Secure Device Manager (SDM)

Each of the TLBs within the TBUs cache frequently used address ranges. By having multiple TBUs, the frequently cached addresses in the TLBs are localized to the masters connected to them. The TCU performs the page table walks on address misses.

The Cortex* -A53 MPCore has its own main and micro translation lookaside buffers (TLBs) for address translation but communicates with the SMMU so that its translation tables remain coherent. For more information about the Cortex* -A53 MPCore MMU, refer to the Cortex* -A53 MPCore chapter.

Figure 11. System Integration