Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 1/25/2024
Public
Document Table of Contents

7.3.3. FPGA-to-HPS Example Transactions

The following section shows some examples of transactions that the FPGA can perform across the FPGA-to-HPS bridge. The interface from the FPGA to the HPS CCU is ACE-Lite. These transactions go through CCU, and their final destination can be directed to either SDRAM memory or OCRAM memory or peripherals. They can be cached or not cached, based on AxCACHE parameters. Transactions could be privileged or non-privileged depending on Memory Allocation.