Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

6.2.9.1.1. Monitors for Mutual Exclusion

The SDRAM scheduler implements support for mutually-exclusive (mutex) accesses on all ports to the SDRAM L3 interconnect.

The process for a mutually-exclusive access is as follows:

  1. A master attempts to lock a memory location by performing an exclusive read from that address.
  2. The master attempts to complete the exclusive operation by performing an exclusive write to the same address location.
  3. The exclusive write access is signaled as:
    • Failed if another master has written to that location between the read and write accesses. In this case the address location is not updated.
    • Successful otherwise.

To support mutually-exclusive accesses, the memory must be configured as normal memory, shareable, or non-cacheable.

Exclusive Access Support

To ensure mutually exclusive access to shared data, use the exclusive access support built into the SDRAM scheduler. The AXI buses that interface to the scheduler provide ARLOCK[0] and AWLOCK[0] signals. The scheduler uses these signals to arbitrate for exclusive access to a memory location. The SDRAM scheduler contains six monitors. The following exclusive-capable masters can use any of the monitors:

  • CPU 0
  • CPU 1
  • CPU 2
  • CPU 3
  • FPGA-to-HPS bridge
  • FPGA-to-SDRAM0 port
  • FPGA-to-SDRAM1 port
  • FPGA-to-SDRAM2 port

Each master can lock only one memory location at a time.