Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 8/15/2024
Public
Document Table of Contents

17.7.1. System Level EMAC Configuration Registers

In addition to the registers in the Ethernet Controller, there are other system level registers in the Clock Manager, System Manager and Reset Manager that must be programmed in order to configure the EMAC and its interfaces.

The following table gives a summary of the important System Manager clock register bits that control operation of the EMAC. These register bits are static signals that must be set while the corresponding EMAC is in reset.

Table 192.  System Manager Clock and Interface Settings
Register.Field Description

emac_global.ptp_clk_sel

1588 PTP reference clock. This bit selects the source of the 1588 PTP reference clock.
  • 0x0= emac_ptp_clk (default from Clock Manager)
  • 0x1=f2h_emac_ptp_ref_clk (from FPGA fabric; in this case, the FPGA must be in usermode with an active reference clock)

emac0.phy_intf_sel

emac1.phy_intf_sel

emac2.phy_intf_sel

PHY Interface Select. These two bits set the PHY mode.
  • 0x0= GMII or MII
  • 0x1= RGMII
  • 0x2= RMII
  • 0x3= RESET (default)

The following table summarizes the important System Manager configuration register bits. All of the fields, except the AXI cache settings, are assumed to be static and must be set before the EMAC is brought out of reset. If the FPGA interface is used, the FPGA must be in user mode and enabled with the appropriate clock signals active before the EMAC can be brought out of reset.

Table 193.  System Manager Static Control Settings
Register.Field Description

fpgaintf_en_3.emac0

fpgaintf_en_3.emac1

fpgaintf_en_3.emac2

FPGA interface to EMAC disable. This field is used to disable signals from the FPGA to the EMAC modules that could potentially interfere with the EMAC's or FPGA's operation.
  • 0x0= Disable (default)
  • 0x1=Enable

emac0.axi_disable

emac1.axi_disable

emac2.axi_disable

AXI Disable. Disables the AXI bus to EMAC.
  • 0x0= Enable (default)
  • 0x1= Disable

emac0.awcache

emac1.awcache

emac2.awcache

emac0.arcache

emac1.arcache

emac2.arcache

EMAC AXI Master AxCACHE settings. It is recommended that these bits are set while the EMAC is idle or in reset.

emac0.awprot

emac1.awprot

emac2.awprot

emac0.arprot

emac1.arprot

emac2.arprot

EMAC Master AxPROT settings. It is recommended that these bits are set while the EMAC is idle or in reset.

emac0.ptp_ref_sel

emac1.ptp_ref_sel

emac2.ptp_ref_sel

Internal/External Timestamp reference. This field selects if the timestamp reference is internally or externally generated. EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2. EMAC0 must be set to internal timestamp; EMAC1 and EMAC2 may be set either to internal or external.
  • 0x0= Internal (default)
  • 0x1= External

Various registers within the Clock Manager must also be configured in order for the EMAC controller to perform properly.

Table 194.  Clock Manager Settings
Register.Field Description

en.emacptpen

emac_ptp_clk output enable.

en.emac0en

en.emac1en

en.emac2en

Enables clock emac0_clk, emac1_clk and emac2_clk output.
Note: There are corresponding ens and enr registers that allow the same fields to be set or cleared on a bit-by-bit basis.
bypass.emacptp

EMAC PTP clock bypass. This bit indicates if the emac_ptp_clk is bypassed to the input clock reference of the peripheral PLL.

  • 0x0= No bypass occurs
  • 0x1= emac_ptp_clk is bypassed to the input clock reference of the main PLL.
Note: There are corresponding bypasss and bypassr registers that allow the same bits to be set or cleared on a bit-by-bit basis.

bypass.emaca

bypass.emacb

Clock Bypass. This bit indicates whether emaca_free_clk or emacb_free_clk is bypassed to the input clock reference of the main PLL.
  • 0x0= No bypass occurs
  • 0x1= emac*_free_clk is bypassed to the input clock reference of the main PLL.
Note: There are corresponding bypasss and bypassr registers that allow the same bits to be set or cleared on a bit-by-bit basis.

emacctl.emac0sel

emacctl.emac1sel

emacctl.emac2sel

EMAC clock source select. This bit selects the source for the emac*clk as either emaca_free_clk or emacb_free clk
  • 0x0= emaca_free_clk
  • 0x1=emacb_free_clk