Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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10.4.4.4.1.1. Single-Bit Error Test for DMA ECC RAM

This sequence tests the single-bit error detection and correction in the ECC decoder of the DMA ECC RAM.
  1. Write data to the ECC_WData3bus through ECC_WData0bus registers.
  2. Set the ECC_EN bit in the CTRL register to enable the ECC detection and correction logic.
  3. Set the DBEN bit in the ECC_dbytectrl register.
  4. Select the address bus to write the data to by programming the ECC_Addrbus register.
  5. In the ECC_accctrl register, program the following bits:
    • RDWR=1
    • ECCOVR=0
    • DATAOVR=1
  6. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
  7. Clear the ECC_EN bit in the CTRL register to disable the ECC detection and correction logic.
  8. Write a data value that has one bit altered in the ECC_WData3bus through ECC_WData0bus registers to the same address.
  9. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
  10. In the ECC_accctrl register, program the following bits:
    • RDWR=0
    • ECCOVR=1
    • DATAOVR=1
  11. Set the ECC_EN bit in the CTRL register to enable the ECC detection and correction logic.
  12. Set the ENBUS* bit in the ECC_startacc register to trigger an indirect write access.
    If you have configured an interrupt to trigger for a single-bit error, then expect it to trigger after these steps have completed. If you read back the data at the same address using the ECC_RData*bus register, expect to see a corrected data result from the memories.