Intel® Stratix® 10 Hard Processor System Technical Reference Manual

ID 683222
Date 11/28/2022
Public

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6.2.9.2.1.2. ECC Read Behavior

When the SDRAM controller reads data from SDRAM, it checks the ECC to determine if the data or address is incorrect. It handles the following cases:

  • If the SDRAM controller finds a single-bit data error, it corrects in the data returned to the master.
    Note: Intel recommends that you enable the SDRAM adapter to write the corrected data back to memory, to avoid uncorrectable double-bit errors.
  • If the SDRAM controller finds a double-bit data error, the SDRAM L3 interconnect issues an interrupt. The ECC hardware cannot correct double-bit errors.
  • If the SDRAM controller finds an error in the address, indicating an address bit upset between the adapter and the hard memory controller, the SDRAM L3 interconnect hardware issues a bus error.