Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
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4.2.4. Transmit and Receive Latencies

Intel uses the following definitions for the transmit and receive latencies for the PCS function with an embedded PMA:
  • Transmit latency is the time the PCS function takes to transmit the first bit on the PMA-PCS interface after the bit was first available on the MAC side interface (MII/GMII).
  • Receive latency is the time the PCS function takes to present the first bit on the MAC side interface (MII/GMII) after the bit was received on the PMA-PCS interface.
Table 33.  PCS Transmit and Receive Latency

For GXB, the TX latencies are obtained from sim:/tb/dut/gmii_tx_d or sim:/tb/dut/mii_tx_d (after clkena is asserted) to sim:/tb/dut/i_tse_pcs_0/tx_frame. The RX latencies are obtained from sim:/tb/dut/gmii_rx_d or sim:/tb/dut/mii_rx_d to sim:/tb/dut/i_tse_pcs_0/tx_frame.

For LVDS, the TX latencies are obtained from the TX latencies are obtained from sim:/tb/dut/gmii_tx_d or sim:/tb/dut/mii_tx_d (after clkena is asserted) to sim:/tb/dut/i_tse_pcs_0/tbi_tx_d_muxed. The RX latencies are obtained from sim:/tb/dut/gmii_rx_d or sim:/tb/dut/mii_rx_d to sim:/tb/dut/i_tse_pcs_0/tbi_rx_d_lvds.

For 2XTBI PCS variant, the TX latencies are obtained from sim:/tb/gmii_tx_d to sim:/tb/tbi2x_tx_d. The RX latencies are obtained from sim:/tb/tbi2x_rx_d to sim:/tb/gmii_rx_d.

For 2XTBI PCS with GXB variant, the TX latencies are obtained from sim:/tb/dut/eth_tse_0_testbench/i_tse_pcs_0/gmii_tx_d to sim:/tb/dut/eth_tse_0_testbench/i_tse_pcs_0/tbi2x_tx_d. The RX latencies are obtained from sim:/tb/dut/eth_tse_0_testbench/i_tse_pcs_0/tbi2x_rx_d to sim:/tb/dut/eth_tse_0_testbench/i_tse_pcs_0/gmii_rx_d.

PCS Configuration Latency (ns)
Transmit Receive
Stratix® IV
10 Mbps SGMII PCS with GXB 3456 1454.85
100 Mbps SGMII PCS with GXB 376 214.8
1000 Mbps SGMII PCS with GXB 104 142.8
1000BASE-X with GXB 8 48
10 Mbps SGMII PCS with LVDS I/O 3064 1720
100 Mbps SGMII PCS with LVDS I/O 384 280
1000 Mbps SGMII PCS with LVDS I/O 136 192
1000BASE-X PCS with LVDS I/O 40 96
Intel® Arria® 10
10 Mbps SGMII PCS with GXB 3600 1867.65
100 Mbps SGMII PCS with GXB 360 187.65
1000 Mbps SGMII PCS with GXB 104 139.65
1000BASE-X with GXB 8 48
10 Mbps SGMII PCS with LVDS I/O 3208 1176
100 Mbps SGMII PCS with LVDS I/O 368 256
1000 Mbps SGMII PCS with LVDS I/O 136 192
1000BASE-X PCS with LVDS I/O 40 96
Intel® Cyclone® 10 GX
10 Mbps SGMII PCS with GXB 3600 1867.65
100 Mbps SGMII PCS with GXB 360 187.65
1000 Mbps SGMII PCS with GXB 104 139.65
1000BASE-X with GXB 8 48
10 Mbps SGMII PCS with LVDS I/O 3208 1176
100 Mbps SGMII PCS with LVDS I/O 368 256
1000 Mbps SGMII PCS with LVDS I/O 136 192
1000BASE-X PCS with LVDS I/O 40 96
Intel® Stratix® 10
10 Mbps SGMII PCS with LVDS I/O 3336 1840
100 Mbps SGMII PCS with LVDS I/O 456 280
1000 Mbps SGMII PCS with LVDS I/O 112 208
1000BASE-X PCS with LVDS I/O with no Enable SGMII 40 104
Intel® Stratix® 10 E-tile
10 Mbps SGMII 2XTBI PCS 4872 6328
100 Mbps SGMII 2XTBI PCS 752 968
1000 Mbps SGMII 2XTBI PCS 300 416
1000BASE-X 2XTBI PCS without enabling SGMII 300 416
10 Mbps SGMII 2XTBI PCS with GXB 6466.401 6160.280
100 Mbps SGMII 2XTBI PCS with GXB 906.401 880.272
1000 Mbps SGMII 2XTBI PCS with GXB 306.401 424.281
1000BASE-X 2XTBI PCS with GXB without enabling SGMII 306.401 424.281
Intel® Agilex™
10 Mbps SGMII PCS with LVDS I/O 2512 2512
100 Mbps SGMII PCS with LVDS I/O 352 232
1000 Mbps SGMII PCS with LVDS I/O 116 192
1000BASE-X PCS with LVDS I/O without enabling SGMII 44 88
10 Mbps SGMII 2XTBI PCS 4872 6328
100 Mbps SGMII 2XTBI PCS 752 968
1000 Mbps SGMII 2XTBI PCS 300 416
1000BASE-X 2XTBI PCS without enabling SGMII 300 416
Intel® Agilex™ E-tile
10 Mbps SGMII 2XTBI PCS with GXB 6466.401 6160.280
100 Mbps SGMII 2XTBI PCS with GXB 906.401 880.272
1000 Mbps SGMII 2XTBI PCS with GXB 306.401 424.281
1000BASE-X 2XTBI PCS with GXB without enabling SGMII 306.401 424.281
Intel® Agilex™ F-tile
1000 Mbps SGMII 2XTBI PCS with FGT 297.79 429.18

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