Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
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7.1.2. MAC and PCS With LVDS Soft-CDR I/O

In configurations that contain the MAC, PCS, and LVDS Soft-CDR I/O, you have the following options in optimizing clock resources:
  • Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance.
  • Utilize the same clock source to drive the reference clock, FIFO transmit and receive clocks, and system clocks, if these clocks run at the same frequency.
Figure 81. Clock Distribution in MAC and SGMII PCS with LVDS Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you can achieve in configurations that contain the MAC, SGMII PCS and LVDS Soft-CDR I/O.


Figure 82. Clock Distribution in MAC and 1000BASE-X PCS with LVDS Configuration—Optimal CaseFigure shows the optimal clock distribution scheme you can achieve in configurations that contain the MAC, 1000BASE-X PCS, and LVDS Soft-CDR I/O.


Notes to Clock Distribution in MAC and SGMII PCS with LVDS Configuration—Optimal Case and Clock Distribution in MAC and 1000BASE-X PCS with LVDS Configuration—Optimal Case:
  1. There may be a performance risk if you use the Triple-Speed Ethernet Intel® FPGA IP variant with LVDS I/O for PMA implementation in Intel® Arria® 10 devices for Intel® Quartus® Prime software versions 17.0.2 and earlier. To avoid the performance risk, Intel® recommends that you regenerate the Triple-Speed Ethernet Intel® FPGA IP and recompile the design in the Intel® Quartus® Prime software version 17.1 or later. To download and install the software patch for Intel® Quartus® Prime version 17.0.2, refer to KDB Link: Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 Devices.
  2. For Intel® Quartus® Prime software version 17.1 onwards, the number of ports supported for Triple-Speed Ethernet design targeting Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices is 8 per instance. To avoid performance risk, you must not promote the reference clock to global clock manually. Assign the number of ports supported and its reference clock to the same I/O bank as inter-bank clock sharing is not allowed.

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