Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.2.5. If_Mode Register (Word Offset 0x14)

Table 54.  IF_Mode Register Description
Bit(s) Name R/W Description
0 SGMII_ENA RW Determines the PCS function operating mode. Setting this bit to 1 enables SGMII mode. Setting this bit to 0 enables 1000BASE-X gigabit mode.
1 USE_SGMII_AN RW This bit applies only to SGMII mode. Setting this bit to 1 causes the PCS function to be configured with the link partner abilities advertised during auto-negotiation. If this bit is set to 0, it is recommended for the PCS function to be configured with the SGMII_SPEED and SGMII_DUPLEX bits.
3:2 SGMII_SPEED[1:0] RW SGMII speed. When the PCS function operates in SGMII mode (SGMII_ENA = 1) and programed not to be automatically configured (USE_SGMII_AN = 0), set the speed as follows:
  • 00: 10 Mbps
  • 01: 100 Mbps
  • 10: 1 Gigabit
  • 11: Reserved

These bits are ignored when SGMII_ENA is 0 or USE_SGMII_AN is 1. These bits are only valid if you only enable the SGMII mode and not the auto-negotiation mode.

4 SGMII_DUPLEX RW SGMII half-duplex mode. Setting this bit to 1 enables half duplex for 10/100 Mbps speed. This bit is ignored when SGMII_ENA is 0 or USE_SGMII_AN is 1. These bits are only valid if you only enable the SGMII mode and not the auto-negotiation mode.
5 SGMII_AN_MODE RW SGMII auto-negotiation mode:
  • 1: enable SGMII PHY mode
  • 0: enable SGMII MAC mode

This bit resets to 0, which defaults to SGMII MAC mode.

15:6 Reserved

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