Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)

Table 43.  IEEE 1588v2 MAC Registers
Dword Offset Name R/W Description HW Reset
0xD0 tx_period RW Clock period for timestamp adjustment on the transmit datapath. The period register is multiplied by the number of stages separating actual timestamp and the GMII bus.
  • Bits 0 to 15: Period in fractional nanoseconds (TX_PERIOD_FNS).
  • Bits 16 to 24: Period in nanoseconds (TX_PERIOD_NS).
  • Bits 25 to 31: Not used.

The default value for the period is 0. For 125 MHz clock, set this register to 8 ns.

0x0
0xD1 tx_adjust_fns RW Static timing adjustment in fractional nanoseconds for outbound timestamps on the transmit datapath.
  • Bits 0 to 15: Timing adjustment in fractional nanoseconds.
  • Bits 16 to 31: Not used.
0x0
0xD2 tx_adjust_ns RW Static timing adjustment in nanoseconds for outbound timestamps on the transmit datapath.
  • Bits 0 to 15: Timing adjustment in nanoseconds.
  • Bits 16 to 23: Not used.
0x0
0xD3 rx_period RW Clock period for timestamp adjustment on the receive datapath. The period register is multiplied by the number of stages separating actual timestamp and the GMII bus.
  • Bits 0 to 15: Period in fractional nanoseconds (RX_PERIOD_FNS).
  • Bits 16 to 24: Period in nanoseconds (RX_PERIOD_NS).
  • Bits 25 to 31: Not used.

The default value for the period is 0. For 125 MHz clock, set this register to 8 ns.

0x0
0xD4 rx_adjust_fns RW Static timing adjustment in fractional nanoseconds for outbound timestamps on the receive datapath.
  • Bits 0 to 15: Timing adjustment in fractional nanoseconds.
  • Bits 16 to 31: Not used.
0x0
0xD5 rx_adjust_ns RW Static timing adjustment in nanoseconds for outbound timestamps on the receive datapath.
  • Bits 0 to 15: Timing adjustment in nanoseconds.
  • Bits 16 to 23: Not used.
0x0

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