Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Document Table of Contents

6.2.5. RGMII Transmit

On transmit, all data transfers are synchronous to both edges of tx_clk. The RGMII control signal tx_control is asserted to indicate the start of a new frame and remains asserted until the last upper nibble of the frame is present on the rgmii_out[3:0] bus. Between frames, tx_control remains deasserted.
Figure 69. RGMII Transmit in 10/100 Mbps

Figure 70. RGMII Transmit in Gigabit Mode

If a frame is received on the Avalon® streaming interface with an error (ff_tx_err asserted with ff_tx_eop), the frame is subsequently transmitted with the RGMII tx_control error signal (at the falling edge of tx_clk) at any time during the frame transfer.

Figure 71. RGMII Transmit with Error in 1000 Mbps

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