Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.3.4. ECC Status Signals

Table 77.  ECC Status Signals
Name I/O Description
pcs_eccstatus[1:0] O Indicates the ECC status. This signal is synchronized to the reg_clk clock domain.

11: An uncorrectable error occurred and the error data appears at the output.

10: A correctable error occurred and the error has been corrected at the output. However, the memory array has not been updated.

01: Not valid.

00: No error.

For more information on the signals, refer to the respective sections shown in References.

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