Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

A.3.1. Pause Frame Generation

When you turn on the Enable full-duplex flow control option, pause frame generation is triggered by the following events:
  • RX FIFO fill level hits the rx_section_empty threshold.
  • XOFF register write.
  • XON register write.
  • XOFF I/O pin (xoff_gen) assertion.
  • XON I/O pin (xon_gen) assertion.

If the RX FIFO buffer is almost full, the MAC function triggers the pause frame generation to the remote Ethernet device.

If the local Ethernet device needs to generate pause frame via XOFF or XON register write or I/O pin assertion, it is recommended to set the rx_section_empty register to a larger value to avoid non-deterministic result.

The following table summarizes the pause frame generation based on the above events.

Table 127.  Pause Frame Generation
Register Write or I/O Pin Assertion (1) Description
XOFF_GEN XON_GEN
1 0 If the XOFF_GEN bit is set to 1, the XOFF pause frames are continuously generated and sent to the MII/GMII TX interface until the XOFF_GEN bit is cleared.
0 1 If the XON_GEN bit is set to 1, the XON pause frames are continuously generated and sent to the MII/GMII TX interface until the XON_GEN bit is cleared.
1 1 This event is not recommended as it will produce non-deterministic result.
Note to Pause Frame Generation :
  1. Set the XON and XOFF registers to 0 when you use the I/O pin to generate the pause frame and vice versa.

Did you find the information on this page useful?

Characters remaining:

Feedback Message