Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.12.3. MII/GMII Clocks and Clock Enablers

Data transfers on the MII/GMII interface are synchronous to the receive and transmit clocks.
Table 108.  MAC Clock Signals
Name I/O Description
rx_clk O Receive clock. This clock is derived from the TBI clock tbi_rx_clk and set to 125 MHz.
tx_clk O Transmit clock. This clock is derived from the TBI clock tbi_tx_clk and set to 125 MHz.
Clock Enabler Signals
Note: The clock enabler signals are present only in SGMII mode.
rx_clkena O Receive clock enabler. In SGMII mode, this signal enables rx_clk.
tx_clkena O Transmit clock enabler. In SGMII mode, this signal enables tx_clk.
Figure 60. Clock Enabler Signal Behavior


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