Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.3.2. Triple-Speed Ethernet System with SGMII

Figure 46.  Triple-Speed Ethernet System with SGMII with Register Initialization Recommendation


Use the following recommended initialization sequences for the example shown in the figure above.

  1. External PHY Initialization using MDIO
  2. PCS Configuration Register Initialization
    1. Set Auto Negotiation Link Timer

      //Set Link timer to 1.6ms for SGMII

      link_timer (address offset 0x12) = 0x0D40

      Link_timer (address offset 0x13) = 0x03

    2. Configure SGMII

      //Enable SGMII Interface and Enable SGMII Auto Negotiation

      //SGMII_ENA = 1, USE_SGMII_AN = 1

      if_mode = 0x0003

    3. Enable Auto Negotiation

      //Enable Auto Negotiation

      //AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 can be ignore

      PCS Control Register = 0x1140

    4. PCS Reset

      //PCS Software reset is recommended where there any configuration changed

      //RESET = 1

      PCS Control Register = 0x9140

      Wait PCS Control Register RESET bit is clear

  3. MAC Configuration Register Initialization
Note:

If 1000BASE-X/SGMII PCS is initialized, set the ETH_SPEED (bit 3) and ENA_10 (bit 25) in command_config register to 0. If half duplex is reported in the PHY/PCS status register, set the HD_ENA (bit 10) to 1 in command_config register.

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