Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Document Table of Contents

5.1. MAC Configuration Register Space

Use the registers to configure the different aspects of the MAC function and retrieve its status and statistics counters.
In multiport MACs, a contiguous register space is allocated for all ports and accessed via the Avalon® memory-mapped control interface. For example, if the register space base address for the first port is 0x00, the base address for the next port is 0x100 and so forth. The registers that are shared among the instances occupy the register space of the first port. Updating these registers in the register space of other ports has no effect on the configuration.
Note: If you select 10/100/1000Mb Ethernet MAC variant and deselect Use clock enable for MAC in the parameter editor of the Triple-Speed Ethernet Intel® FPGA IP, the CSR access latency will be dependent on the datapath clock frequency.
Table 37.  Overview of MAC Register Space
Dword Offset Section Description
0x00 – 0x17 Base Configuration Base registers to configure the MAC function. At the minimum, you must configure the following functions:
  • Primary MAC address (mac_0/mac_1)
  • Enable transmit and receive paths (TX_ENA and RX_ENA bits in the command_config register)

The following registers are shared among all instances of a multiport MAC:

  • rev
  • scratch
  • frm_length
  • pause_quant
  • mdio_addr0 and mdio_addr1
  • tx_ipg_length

For more information about the base configuration registers, refer to Base Configuration Registers (Dword Offset 0x00 – 0x17).

0x18 – 0x38 Statistics Counters Counters collecting traffic statistics. For more information about the statistics counters, refer to Statistics Counters (Dword Offset 0x18 – 0x38).
0x3A Transmit Command Transmit and receive datapaths control register. For more information about these registers, see Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B).
0x3B Receive Command
0x3C – 0x3E Extended Statistics Counters Upper 32 bits of selected statistics counters. These registers are used if you turn on the option to use extended statistics counters. For more information about these counters, refer to Statistics Counters (Dword Offset 0x18 – 0x38).
0x3F Reserved 12 Unused.
0x40 – 0x7F Multicast Hash Table 64-entry write-only hash table to resolve multicast addresses. Only bit 0 in each entry is significant. When you write a 1 to a dword offset in the hash table, the MAC accepts all multicast MAC addresses that hash to the value of the address (bits 5:0). Otherwise, the MAC rejects the multicast address. This table is cleared during reset.

Hashing is not supported in 10/100 and 1000 Mbps small MAC variations.

0x80 – 0x9F MDIO Space 0

or PCS Function Configuration

MDIO Space 0 and MDIO Space 1 map to registers 0 to 31 of the PHY devices whose addresses are configured in the mdio_addr0 and mdio_addr1 registers respectively. For example, register 0 of PHY device 0 maps to dword offset 0x80, register 1 maps to dword offset 0x81 and so forth.

Reading or writing to MDIO Space 0 or MDIO Space 1 immediately triggers a corresponding MDIO transaction to read or write the PHY register. Only bits [15:0] of each register are significant. Write 0 to bits [31:16] and ignore them on reads.

If your variation does not include the PCS function, you can use MDIO Space 0 and MDIO Space 1 to map to two PHY devices.

If your MAC variation includes the PCS function, the PCS function is always device 0 and its configuration registers (PCS Configuration Register Space) occupy MDIO Space 0. You can use MDIO Space 1 to map to a PHY device.

0xA0 – 0xBF MDIO Space 1
0xC0 – 0xC7 Supplementary Address Supplementary unicast addresses. For more information about these addresses, refer to Supplementary Address (Dword Offset 0xC0 – 0xC7).
0xC8 – 0xCF Reserved 12 Unused.
0xD0 – 0xD6 IEEE 1588v2 Feature Registers to configure the IEEE 1588v2 feature. For more information about these registers, refer to IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6).
0xD7 – 0xE0 Reserved 12 Unused.
0xE1 – 0xE3 Deterministic Latency Configuration and status registers to retrieve the status and access the latency values returned by the deterministic latency module. For more information about these registers, refer to Deterministic Latency (Dword Offset 0xE1– 0xE3).
12 Intel recommends that you set all bits in the reserved registers to 0 and ignore them on reads.

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