Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

3.1. Core Configuration

Table 18.  Core Configuration Parameters
Name Value Description
Core Variation
  • 10/100/1000 Mb Ethernet MAC
  • 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS
  • 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS 2 3 4
  • 1000BASE-X/SGMII PCS only
  • 1000BASE-X/SGMII 2XTBI PCS only2 5
  • 1000 Mb Small MAC
  • 10/100 Mb Small MAC
Determines the primary blocks to include in the variation.
Enable ECC protection On/Off Turn on this option to enable ECC protection for internal memory blocks.
Interface
  • MII
  • GMII
  • RGMII
  • MII/GMII
Determines the Ethernet-side interface of the MAC block.
  • MII—The only option available for 10/100 Mb Small MAC core variations.
  • GMII—Available only for 1000 Mb Small MAC core variations.
  • RGMII—Available for 10/100/1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations.
  • MII/GMII—Available only for 10/100/1000 Mb Ethernet MAC core variations. If this is selected, media independent interface (MII) is used for the 10/100 interface, and gigabit media independent interface (GMII) for the gigabit interface.
Note:
  1. The RGMII interface is not supported in Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices from Intel® Quartus® Prime software version 17.1 onwards.
  2. For Cyclone® V devices, the timing closure is subject to the ability to close timing with external PHY peripherals. Intel recommends –6 or –7 speed grade part, and timing analysis is required to ensure that the selected speed grade meets the timing closure according to the external PHY peripherals specification. Intel does not recommend –8 speed grade part for RGMII interface.
Use clock enable for MAC On/Off Turn on this option to include clock enable signals for the MAC. This option is only applicable for 10/100/1000Mb Ethernet MAC and 1000Mb Small MAC core variations.
Use internal FIFO On/Off Turn on this option to include internal FIFO buffers in the core. You can only include internal FIFO buffers in single-port MACs.
Number of ports 1, 4, 8, 12, 16, 20, and 24 Specifies the number of Ethernet ports supported by the IP. This parameter is enabled if the parameter Use internal FIFO is turned off. A multiport MAC does not support internal FIFO buffers.
Note: For Intel® Quartus® Prime software version 17.1 onwards, the number of ports supported for Triple-Speed Ethernet designs targeting Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices is 8. This is applicable only when you select LVDS I/O for the Transceiver type option.
Transceiver type
  • None
  • LVDS I/O
  • GXB
  • FGT
This option is only available for variations that include the PCS block.
  • None—the PCS block does not include an integrated transceiver module. The PCS block implements a ten-bit interface (TBI) to an external SERDES chip.
  • LVDS I/O, GXB, or FGT—the IP includes an integrated transceiver module to implement a 1.25 Gbps transceiver.
    • Respective GXB module is included for target devices with GX transceivers.
    • For target devices with LVDS I/O including Soft-CDR such as Stratix® III devices, the ALTLVDS module is included. Starting from Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices, the module included is changed to LVDS SERDES.
    • GXB and LVDS I/O options are not available for Intel® Cyclone® 10 LP devices.
    • For Intel® Stratix® 10 and Intel® Agilex™ devices, the GXB option is available only in the Intel FPGA devices with E-tile transceivers.
    • For Intel® Agilex™ devices, the FGT option is available only in the Intel FPGA devices with F-tile transceivers.
Note: There may be a performance risk if you use the Triple-Speed Ethernet Intel® FPGA IP variant with LVDS I/O for PMA implementation in the Intel® Arria® 10 devices for Intel® Quartus® Prime software version 17.0.2 and earlier. To avoid the performance risk, Intel® recommends that you regenerate the Triple-Speed Ethernet Intel® FPGA IP and recompile the design in the Intel® Quartus® Prime software version 17.1 or later. To download and install the software patch for Intel® Quartus® Prime version 17.0.2, refer to KDB link: Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 Devices.
2 This variation is only supported when you select Intel® Stratix® 10 devices with E-tile transceivers or Intel® Agilex™ devices with E-tile or F-tile transceivers in the Intel® Quartus® Prime Pro Edition software.
3 You can only turn off Use internal FIFO option for this variation when you select Intel® Stratix® 10 devices with E-tile transceivers is selected starting from Intel® Quartus® Prime software version 20.4.
4 Embedded PMA is included and is not optional when you turn on the Use internal FIFO option for this variation. However, the embedded PMA is excluded when you turn off Use internal FIFO. You must manually connect the variant to the E-tile transceiver or external PHY that supports the 2XTBI interface.
5 Embedded PMA is excluded. You must manually connect the variant to the E-tile or external PHY that supports 2XTBI interface.

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