Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

4.1.1. MAC Architecture

Figure 12. 10/100/1000 Ethernet MAC With Internal FIFO Buffers


The FIFO buffers, which you can configure to 8 or 32 bits wide, store the transmit and receive data. The buffer width determines the data width on the Avalon® streaming receive and transmit interfaces. You can configure the FIFO buffers to operate in cut-through or store-and-forward mode using the rx_section_full and tx_section_full registers.

Figure 13. Multiport MAC Without Internal FIFO Buffers


In a multiport MAC, the instances share the MDIO master and some configuration registers. You can use the Avalon® Streaming Multi-Channel Shared Memory FIFO core in the Platform Designer to store the transmit and receive data.

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