Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.11.7. IEEE 1588v2 PHY Path Delay Interface Signals

Table 104.  IEEE 1588v2 PHY Path Delay Interface Signals
Signal I/O Width Description
tx_path_delay_data I 22 Use this bus to carry the path delay on the transmit datapath. The delay is measured between the physical network and MII/GMII to adjust the egress timestamp.

Bits 0 to 9—Fractional number of clock cycles

Bits 10 to 21—Number of clock cycles

rx_path_delay_data I 22 Use this bus to carry the path delay on the receive datapath. The delay is measured between the physical network and MII/GMII to adjust the ingress timestamp.

Bits 0 to 9—Fractional number of clock cycles

Bits 10 to 21—Number of clock cycles

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