Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals

Figure 53. 10/100/1000 Ethernet MAC Function Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
Table 83.  References
Interface Signal Section
Clock and reset signals Reset Signals
MAC receive interface signals Multiport MAC Receive Interface Signals
MAC transmit interface signals Multiport MAC Transmit Interface Signals
MAC packet classification signals Multiport MAC Packet Classification Signals
MAC FIFO status signals Multiport MAC FIFO Status Signals
Magic packet signals Pause and Magic Packet Signals
Status LED signals Status LED Control Signals
MAC control interface signals MAC Control Interface Signals
Ten-bit interface signals TBI Interface Signals

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