Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

1.7. IP Verification

For each release, Intel verifies the Triple-Speed Ethernet Intel® FPGA IP through extensive simulation and internal hardware verification in various Intel FPGA device families. The University of New Hampshire InterOperability Lab also successfully verified the IP prior to its release.

Intel used a highly parameterizeable transaction-based testbench to test the following aspects of the IP:

  • Register access
  • MDIO access
  • Frame transmission and error handling
  • Frame reception and error handling
  • Ethernet frame MAC address filtering
  • Flow control
  • Retransmission in half-duplex

Intel has also validated the Triple-Speed Ethernet Intel® FPGA IP in both optical and copper platforms using the following development kits:

  • Nios® II Development Kit, Cyclone® II Edition (2C35)
  • Intel® Arria® 10 FPGA Development Kit
  • Intel® Cyclone® 10 LP FPGA Development Kit
  • Stratix® III FPGA Development Kit
  • Stratix® IV FPGA Development Kit
  • Stratix® V FPGA Development Kit
  • Intel® Stratix® 10 FPGA Development Kit
  • Quad 10/100/1000 Marvell PHY
  • MorethanIP 10/100 and 10/100/1000 Ethernet PHY Daughtercards

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