Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

4.1.10. MAC Error Correction Code (ECC)

The error correction code (ECC) feature is implemented to the memory instances in the IP. This feature is capable of detecting single and double bit errors, and can fix single bit errors in the corrupted data.
Note: This feature is only applicable for Arria® V GZ, Stratix® V, and Intel® Arria® 10 devices.
Table 30.  IP Variation and ECC Protection Support
IP Variation ECC Protection Support
10/100/1000 Mb Ethernet MAC Protects the following options:
  • Transmit and receive FIFO buffer
  • Retransmit buffer (if half duplex is enabled)
  • Statistic counters (if enabled)
  • Multicast hashtable (if enabled)
10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS Protects the following options:
  • Transmit and receive FIFO buffer
  • Retransmit buffer (if half duplex is enabled)
  • Statistic counters (if enabled)
  • Multicast hashtable (if enabled)
  • SGMII bridge (if enabled)
1000BASE-X/SGMII PCS only Protects the SGMII bridge (if enabled).
1000 Mb Small MAC Protects the transmit and receive FIFO buffer.
10/100 Mb Small MAC Protects the following options:
  • Transmit and receive FIFO buffer
  • Retransmit buffer (if half duplex is enabled)

When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and 1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the IP.

  • Single channel core configuration—eccstatus[1:0] output ports.
  • Multi-channel core configuration—eccstatus_<n>[1:0] output ports, where eccstatus_0[1:0] is for channel 0, eccstatus_1[1:0] for channel 1, and so on.

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