Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

9.3. Testbench Verification

The testbench is self-checking and determines the success of a simulation by verifying the frames received. It also checks for any errors detected by the frame monitors. The testbench does not verify the IEEE statistics generated by the MAC layer. Simulation fails only if the testbench is not able to detect deliberately inserted errors. At the end of a simulation, the testbench displays messages in the simulator console indicating its results.

The testbench verifies the following functionality:

  • Transmit and receive datapaths are functionally correct.
  • Ethernet frames generated by the frame generator are received by the frame monitor.
  • Additional checks for configurations that contain the MAC function:
    • Correct CRC-32 is inserted.
    • Short frames are padded up to at least 64 bytes in length.
    • Untagged received frames of size greater than the maximum frame length are truncated to the maximum frame length with additional bytes up to 12.
    • CRC-32 is optionally discarded before the frames are received by the traffic monitor.
  • Additional checks for configurations that contain the PCS function with optional embedded PMA:
    • Transmit frames generated by the frame generator are correctly encapsulated.
    • Received frames are de-encapsulated before they are forwarded to the frame monitor.

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