2.2.1. Design Constraint File No Longer Generated
For a new Triple-Speed Ethernet Intel® FPGA IP created using the Intel® Quartus® Prime software version 13.0 or later, the software no longer generate the <variation_name>_constraints.tcl file that contains the necessary constraints for the compilation of your IP variation.
The following table lists the recommended Intel® Quartus® Prime pin assignments that you can set in your design.
|Pin Assignment||Assignment Value||Description||Design Pin|
|FAST_INPUT_REGISTER||ON||To optimize I/O timing for MII, GMII and TBI interface.||MII, GMII, RGMII, TBI input pins.|
|FAST_OUTPUT_REGISTER||ON||To optimize I/O timing for MII, GMII and TBI interface.||MII, GMII, RGMII, TBI output pins.|
|IO_STANDARD||1.4-V PCML or 1.5-V PCML||I/O standard for GXB serial input and output pins.||GXB transceiver serial input and output pins.|
|IO_STANDARD||LVDS||I/O standard for LVDS/IO serial input and output pins.||LVDS/IO transceiver serial input and output pins.|
|GLOBAL_SIGNAL||Global clock||To assign clock signals to use the global clock network. Use this setting to guide the Intel® Quartus® Prime software in the fitter process for better timing closure.||
|GLOBAL_SIGNAL||Regional clock||To assign clock signals to use the regional clock network. Use this setting to guide the Intel® Quartus® Prime software in the fitter process for better timing closure.||
|GLOBAL_SIGNAL||OFF||To prevent a signal to be used as a global signal.||Signals for Arria® V devices:
Did you find the information on this page useful?