Triple-Speed Ethernet Intel® FPGA IP User Guide

Download
ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.2.1. Avalon Streaming Receive Interface

Figure 63. Receive Operation—MAC With Internal FIFO Buffers


Figure 64. Receive Operation—MAC Without Internal FIFO Buffers


Figure 65. Invalid Length Error During Receive Operation—MAC With Internal FIFO Buffer


Figure 66. Invalid Length Error During Receive Operation—MAC Without Internal FIFO Buffers


Did you find the information on this page useful?

Characters remaining:

Feedback Message