Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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9.4. Testbench Configuration

The testbench is configured, by default, to operate in loopback mode. Frames sent through the transmit path are looped back into the receive path.

Separate data paths can be configured for single-channel MAC with internal FIFO buffers. In this configuration, the MII/GMII Ethernet frame generator is enabled and the testbench control block simulates independent yet complete receive and transmit datapaths.

You can also customize other aspects of the testbench using the testbench simulation parameters.

The device under test is configured with the following default settings:

  • Link speed is set to Gigabit except for configurations that contain Small MAC. For Small MACs, the default speed is 100 Mbps.
  • Five Ethernet frames of payload length 100, 101, 102, 103 and 104 bytes are transmitted to the system-side interface and looped back on the ethernet-side interface.
  • Default settings for the MAC function:
    • The command_config register is set to 0x0408003B.
    • Promiscuous mode is enabled.
    • The maximum frame length, register frm_length, is configured to 1518.
    • For a single-channel MAC with internal FIFO buffers, the transmit FIFO buffer is set to start data transmission as soon as its level reaches tx_section_full. The receive FIFO buffer is set to begin forwarding Ethernet frames to the Avalon streaming receive interface when its level reaches rx_section_full.
  • Default setting for the PCS function:
    • The if_mode register is set to 0x0000.
    • Auto-negotiation between the local PHY and remote link PHY is bypassed.

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