Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.2.3. Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)

The definition of each field in the partner_ability registers depends on the mode in which the PCS function operates.

In this mode, the definition of the fields in the dev_ability register are the same as the fields in the partner_ability register. The contents of these registers are valid only when the auto-negotiation completes (AUTO_NEGOTIATION_COMPLETE bit in the status register = 1).

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