Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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6.1.1.7. Pause and Magic Packet Signals

The pause and magic packet signals are component-specific signals.
Table 64.  Pause and Magic Packet Signals
Name I/O Description
xon_gen I Assert this signal for at least 1 tx_clk clock cycle to trigger the generation of a pause frame with a 0 pause quanta. The MAC function generates the pause frame independent of the status of the receive FIFO buffer.

This signal is not in use in the following conditions:

  • Ignored when the xon_gen bit in the command_config register is set to 1.
  • Absent when the Enable full duplex flow control option is turned off.
xoff_gen I Assert this signal for at least one tx_clk clock cycle to trigger the generation of a pause frame with a pause quanta configured in the pause_quant register. The MAC function generates the pause frame independent of the status of the receive FIFO buffer.

This signal is not in use in the following conditions:

  • Ignored if the xoff_gen bit in the command_config register is set to 1.
  • Absent when the Enable full duplex flow control option is turned off.
magic_sleep_n I Assert this active-low signal to put the node into a power-down state.

If magic packets are supported (the MAGIC_ENA bit in the command_config register is set to 1), the receiver logic stops writing data to the receive FIFO buffer and the magic packet detection logic is enabled. Setting this signal to 1 restores the normal frame reception mode.

This signal is present only if the Enable magic packet detection option is turned on.

magic_wakeup O If the MAC function is in the power-down state, the MAC function asserts this signal to indicate that a magic packet has been detected and the node is requested to restore its normal frame reception mode.

This signal is present only if the Enable magic packet detection option is turned on.

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