7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O
For Intel® Agilex™ devices, you must adhere to the following LVDS soft-CDR placement guidelines to avoid Quartus design compilation fitter error:
- In each GPIO bank of the Intel® Agilex™ FPGA device, there are two sub-banks. The top sub-bank has pin indexes from 48-95 and supports a maximum of 4 LVDS soft-CDR I/O. The bottom sub-bank has pin indexes from 0-47 and supports a maximum of 8 LVDS soft-CDR I/O.
- For the exact location of the LVDS soft-CDR I/O pin, refer to the Intel® Agilex™ device pin-out files.
- One Triple-Speed Ethernet IP cannot support LVDS soft-CDR I/O that has a mixture channel placement in both top and bottom sub-banks. You must constrain the LVDS soft-CDR I/O channel placement to either the top sub-bank or bottom sub-bank only.
For Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices, you cannot share PLLs for designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with LVDS soft-CDR I/O. The Intel® Quartus® Prime software will not merge the PLLs for these instances. Therefore, each of the design instance must be implemented in a different I/O bank with a dedicated clock path.
For older devices, you can optimize the resource utilization by sharing the PLLs for designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with LVDS soft-CDR I/O.
The Intel® Quartus® Prime software merges the PLLs for these instances if you implement the following items in your design:
- Connect the reference clock of each instance to the same source.
- Place the LVDS I/O pins on the same side of the FPGA.
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