Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.11.6. IEEE 1588v2 PCS Phase Measurement Clock Signal

Table 103.  IEEE 1588v2 PCS Phase Measurement Clock Signal
Signal I/O Width Description
pcs_phase_measure_clk I 1 Sampling clock to measure the latency through the PCS FIFO buffer. The recommended frequency is 80 MHz.