Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Document Table of Contents

8.1. Creating Clock Constraints

After you generate and integrate the Triple-Speed Ethernet Intel® FPGA IP into the system, you need to create a timing constraints file to specify the clock constraint requirement.

You can specify the clock requirement in the timing constraint file using the following command:


For example, for a new clock named "reg_clk", with a 50 MHz clock targeted to the top level input port "clk", enter the following command line:

create_clock -name "reg_clk" -period "50 MHz" [get_ports "clk"]

Figure below shows an example of how you can create a timing constraint file to constrain the Triple-Speed Ethernet Intel® FPGA IP clocks.

Figure 85.  Triple-Speed Ethernet Timing Constraint ExampleThe reconfig_clk signal is not shown in this example. Constrain the reconfig_clk based on your design implementation.

The example above consists of the following Verilog modules:

  • TOP.v—The top level design module which contains an Intel® FPGA PLL and a user-defined instance. The top level input clocks consist of pll_inclk, ext_clk, and xcvr_ref_clk.
  • user_instance.v—The user-defined instance that instantiates the Triple-Speed Ethernet Intel® FPGA IP.
  • tse_variation.v—A Triple-Speed Ethernet Intel® FPGA IP variation. This example uses a 10/100/1000-Mbps Ethernet MAC with an internal FIFO buffer, a 1000BASE-X/SGMII PCS, and an embedded PMA.

The frequency for the PLL clock input, inclk0, is 100 MHz, and the frequency for the PLL clock output, c0, is 100 MHz. The Triple-Speed Ethernet MAC Avalon streaming clocks, ff_tx_clk and ff_rx_clk, use c0 as the clock source. The input clock frequency for the transceiver reference clock, xcvr_ref_clk, is 125 MHz.

Example of the Triple-Speed Ethernet IP timing constraint file:

# PLL clock input, 100 MHz
create_clock -name pll_inclk -period 10.000 [get_ports {pll_inclk}]

# ext_clk, 50 MHz
create_clock -name ext_clk -period 20.000 [get_ports {ext_clk}]

# xcvr_ref_clk, 125 MHz
create_clock -name xcvr_ref_clk -period 8.000 [get_ports {xcvr_ref_clk}]

# Derive PLL generated output clocks.
Note: The derive_pll_clocks command is not supported in Intel® Stratix® 10 devices because all PLL clocks are automatically generated by the SDC files generated alongside the PLL IP.

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