Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 11/25/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3. FIFO Options

The FIFO options are enabled only for MAC variations that include internal FIFO buffers.
Table 20.  FIFO Options Parameters
Name Value Parameter
Width 8 Bits and 32 Bits Determines the data width in bits of the transmit and receive FIFO buffers.
Transmit Between 64 and 64K Determines the depth of the internal FIFO buffers.