Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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4.1.5. MAC Transmit and Receive Latencies

Intel uses the following definitions for the transmit and receive latencies:
  • Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon® streaming interface.
  • Receive latency is the number of clock cycles the MAC function takes to present the first bit on the Avalon® streaming interface after the bit was received on the network-side interface (MII/GMII/RGMII).
Table 27.  Transmit and Receive Nominal LatencyThe transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the typical values specified in this user guide when deriving the latencies. Under MAC Options tab, only the following options are selected when deriving the latencies shown in the table below: Enable MAC 10/100 half duplex support, Include statistics counters, and Enable magic packet detection.
MAC Configuration Latency (Clock Cycles) 6 7
Transmit Receive
MAC with Internal FIFO Buffers 8
GMII in gigabit and cut-through mode 38 99
MII in 100M and cut-through mode 40 184
MII in 10M and cut-through mode 34 183
RGMII in gigabit and cut-through mode 40 102
RGMII in 10 Mbps and cut-through mode 41 187
RGMII in 100 Mbps and cut-through mode 36 186
MAC without Internal FIFO Buffers 9
GMII 15 28
MII 26 56
RGMII in gigabit mode 16 31
RGMII in10/100 Mbps 27 59
6 The clocks in all domains are running at the same frequency.
7 The numbers in this table are from simulation.
8 The data width is set to 32 bits
9 The data width is set to 8 bits.

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