Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.1.7. IEEE 1588v2 Feature PMA Delay

PMA digital and analog delay of hardware for the IEEE 1588v2 feature and the register timing adjustment. 1 UI is equivalent to 800 ps.
Table 45.  IEEE 1588v2 Feature PMA Delay—Hardware
Delay Device Timing Adjustment
TX register RX register
Digital Stratix® V or Arria® V GZ 53 UI 26 UI
Arria® V GX, Arria® V GT, or Arria® V SoC 52 UI 34 UI
Cyclone® V GX or Cyclone® V SoC 32 UI 44 UI
Intel® Arria® 10 43 UI 24.5 UI
Analog Stratix® V -1.1 ns 1.75 ns
Arria® V -1.1 ns 1.75 ns
Cyclone® V -1.1 ns 1.75 ns
Table 46.  IEEE 1588v2 Feature LVDS I/O Delay—Hardware
Delay Device Timing Adjustment
TX register RX register
Digital Stratix® V or Arria® V GZ 21 UI 26 UI
Arria® V GX, Arria® V GT, or Arria® V SoC 21 UI 26 UI
Intel® Arria® 10 21 UI 26 UI
Intel® Stratix® 10 (L-tile and H-tile) 21 UI 26 UI

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