Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.1.5. MAC Receive Interface Signals

Table 60.  MAC Receive Interface Signals
Name Avalon Streaming 
Signal Type I/O Description
Avalon Streaming Signals
ff_rx_clk

(In Platform Designer: receive_clock_connection)

clk I Receive clock. All signals on the Avalon streaming receive interface are synchronized on the rising edge of this clock. Set this clock to the frequency required to get the desired bandwidth on this interface. This clock can be completely independent from rx_clk.
ff_rx_dval valid O Receive data valid. When asserted, this signal indicates that the data on the following signals are valid: ff_rx_data[(DATAWIDTH -1):0], ff_rx_sop, ff_rx_eop, rx_err[5:0], rx_frm_type[3:0], and rx_err_stat[17:0].
ff_rx_data
[(DATAWIDTH-1):0] data O Receive data. When DATAWIDTH is 32, the first byte received is ff_rx_data[31:24] followed by ff_rx_data[23:16] and so forth.
ff_rx_mod[1:0] empty O Receive data modulo. Indicates invalid bytes in the final frame word:
  • 11: ff_rx_data[23:0] is not valid
  • 10: ff_rx_data[15:0] is not valid
  • 01: ff_rx_data[7:0] is not valid
  • 00: ff_rx_data[31:0] is valid

This signal applies only when DATAWIDTH is set to 32.

ff_rx_sop startofpacket O Receive start of packet. Asserted when the first byte or word of a frame is driven on ff_rx_data[(DATAWIDTH-1):0].
ff_rx_eop endofpacket O Receive end of packet. Asserted when the last byte or word of frame data is driven on ff_rx_data[(DATAWIDTH-1):0].
ff_rx_rdy ready I Receive application ready. Assert this signal on the rising edge of ff_rx_clk when the user application is ready to receive data from the MAC function.
rx_err[5:0] error O Receive error. Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame. See rx_err Bit Description for the bit description.
Component-Specific Signals
ff_rx_dsav O Receive frame available. When asserted, this signal indicates that the internal receive FIFO buffer contains some data to be read but not necessarily a complete frame. The user application may want to start reading from the FIFO buffer.

This signal remains deasserted in the store and forward mode.

rx_frm_type[3:0] O Frame type. See rx_frm_type Bit Description for the bit description.
ff_rx_a_full O Asserted when the FIFO buffer reaches the almost-full threshold.
ff_rx_a_empty O Asserted when the FIFO buffer goes below the almost-empty threshold.
rx_err_stat[17:0] O rx_err_stat[17]: One indicates that the receive frame is a stacked VLAN frame.

rx_err_stat[16]: One indicates that the receive frame is either a VLAN or stacked VLAN frame.

rx_err_stat[15:0]: The value of the length/type field of the receive frame.

Table 61.   rx_frm_type Bit Description
Bit Description
3 Indicates VLAN frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.
2 Indicates broadcast frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.
1 Indicates multicast frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.
0 Indicates unicast frames. Asserted with ff_rx_sop and remains asserted until the end of the frame.
Table 62.  rx_err Bit Description
Bit Description
5 Collision error. Asserted when the frame was received with a collision.
4 Corrupted receive frame caused by PHY or PCS error. Asserted when the error is detected on the MII/GMII/RGMII.
3 Truncated receive frame. Asserted when the receive frame is truncated due to an overflow in the receive FIFO buffer.
2 16 CRC error. Asserted when the frame is received with a CRC-32 error. This error bit applies only to frames with a valid length. Refer to Length Checking.
1 16 Invalid length error. Asserted when the receive frame has an invalid length as defined by the IEEE Standard 802.3. For more information on the frame length, refer to Length Checking.
0 Receive frame error. Indicates that an error has occurred. It is the logical OR of rx_err[5:1].
16 Bits 1 and 2 are not mutually exclusive. Ignore CRC error rx_err[2] signal if it is asserted at the same time as the invalid length error rx_err[1] signal.

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