Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.10.4. SERDES Control Signals

These signals apply only to PMA blocks implemented in devices with GX transceivers.
Table 95.  SERDES Control Signal
Name I/O Description
rx_recovclkout O Recovered clock from the PMA block.
pcs_pwrdn_out O Power-down status. Asserted when the PCS function is in power-down mode; deasserted when the PCS function is operating in normal mode. This signal is implemented only when an internal SERDES is used with the option to export the power-down signal.

This signal is not present in PMA blocks implemented in Intel® Arria® 10, Stratix® V, Arria® V, and Arria® V devices with GX transceivers.

gxb_pwrdn_in I Power-down enable. Assert this signal to power down the transceiver quad block. This signal is implemented only when an internal SERDES is used with the option to export the power-down signal.

This signal is not present in PMA blocks implemented in Intel® Arria® 10, Stratix® V, Arria® V, and Arria® V devices with GX transceivers.

gxb_cal_blk_clk I Calibration block clock for the ALT2GXB module (SERDES). This clock is typically tied to the 125 MHz ref_clk. Only implemented when an internal SERDES is used.

This signal is not present in PMA blocks implemented in Intel® Arria® 10, Stratix® V, Arria® V, and Cyclone® V devices with GX transceivers.

reconfig_clk I Reference clock for the dynamic reconfiguration controller. If you use a dynamic reconfiguration controller in your design to dynamically control the transceiver, both the reconfiguration controller and the IP require this clock. This clock must operate between 37.5–50 MHz. Tie this clock low if you are not using an external reconfiguration controller.

This signal is not present in PMA blocks implemented in Intel® Arria® 10, Stratix® V, Arria® V, and Cyclone® V devices with GX transceivers.

reconfig_togxb[n:0] I Driven from an external dynamic reconfiguration controller. Supports the selection of multiple transceiver channels for dynamic reconfiguration.

For PMA blocks implemented in Stratix® V devices with GX transceivers, the bus width is [139:0]. For more information about the bus width for PMA blocks implemented in each device, refer to the Dynamic Reconfiguration chapter of the respective device handbook.

reconfig_fromgxb[n:0] O Connects to an external dynamic reconfiguration controller. The bus identifies the transceiver channel whose settings are being transmitted to the reconfiguration controller. Leave this bus disconnected if you are not using an external reconfiguration controller.

For more information about the bus width for PMA blocks implemented in each device, refer to the Dynamic Reconfiguration chapter of the respective device handbook.

reconfig_busy I Driven from an external dynamic reconfiguration controller. This signal will indicate the busy status of the dynamic reconfiguration controller during offset cancellation. Tie this signal to 1'b0 if you are not using an external reconfiguration controller.

This signal is not present in PMA blocks implemented in Intel® Arria® 10, Stratix® V, Arria® V, and Arria® V devices with GX transceivers.

For more information on the signals, refer to the respective sections shown in References.

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