Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

4.1.11. MAC Reset

A hardware reset resets all logic. A software reset only disables the transmit and receive paths, clears all statistics registers, and flushes the receive FIFO buffer. The values of configuration registers, such as the MAC address and thresholds of the FIFO buffers, are preserved during a software reset.

When you trigger a software reset, the MAC function sets the TX_ENA and RX_ENA bits in the command_config register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only disabled when the current frame transmission and reception complete.

  • To trigger a hardware reset, assert the reset signal.
  • To trigger a software reset, set the SW_RESET bit in the command_config register to 1. The SW_RESET bit is cleared automatically when the software reset ends.

Intel recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating speed or mode without changing other configurations, preserve the command_config register before performing the software reset and restore the register after the changing the MAC operating speed or mode.

Figure 19. Software Reset Sequence


Note: If the SW_RESET bit is 1 when the line clocks are not available (for example, cable is disconnected), the statistics registers may not be cleared.

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