Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

4.4. Deterministic Latency

The Deterministic Latency (DL) term used across this document refers to the ability to precisely determine the delay between the elastic FIFO (EFIFO) and the PMA pins.

The deterministic latency measurement methodology is introduced for Intel® Stratix® 10 E-tile devices. It is based on the concept of measuring the time when a given word is at the interface to the PMA and when that same word is at the FPGA core. The difference in time between these two events, when added to the PMA propagation delay, determines the total latency between the FPGA core and the serial pins. Such a calculation intrinsically includes all delays due to intermediate logic, FIFOs, and all other effects.

Figure 43. Deterministic Latency High Level Block Diagram

Even though this measurement is applicable for E-tile devices, Triple-Speed Ethernet only supports this feature for the 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2xTBI PCS and without internal FIFO enabled IP variant using Intel® Stratix® 10 E-tile devices, running at 1G speed. You must turn on Enable timestamping and Enable deterministic latency for E-tile device options to enable the DL feature.

Table 35.  Deterministic Latency Parameter Description for Triple-Speed Ethernet This table shows parameter description for the deterministic latency measurement for Triple-Speed Ethernet use case.
Item Value Description
sampling_clk period 4.375 ns Period for sampling clock (i_dl_sampling_clk) of 228.571429 MHz.
UI period 0.8 ns Period for unit interval.
parallel_clk 20 UI Period for 1 parallel clock cycle.
tx_delay (TxDL) Read from EFIFO-DL register 0xE2[20:0]

TX delay value in sampling_clk cycles, fixed point format Q13.8.

Bit [20:8] is integer, bit [7:0] is fractional number.

For example, tx_delay = 0x27F4,

Bit [20:8] = 0x27 = 39

Bit [7:0] = 0xF4 = 0.953125

Hence, tx_delay = 39.953125 clock cycles.

rx_delay (RxDL) Read from EFIFO-DL register 0xE3[20:0]

RX delay value in the sampling_clk cycles, fixed point format Q13.8.

Bit [20:8] is integer, bit [7:0] is fractional number.

For example, rx_delay = 0x27F4,

Bit [20:8] = 0x27 = 39

Bit [7:0] = 0xF4 = 0.953125

Hence, tx_delay = 39.953125 clock cycles.

Table 36.  Deterministic Latency Measurement for Triple-Speed Ethernet This table shows the TX and RX latency calculations for the 1G variant.
Variant TX Latency (ns) RX Latency (ns)
1G TxDL * (sampling_clock period in ns)/(2^8) + (225 * UI period in ns) RxDL * (sampling_clock period in ns)/(2^8) + (-45) * (UI period in ns)
Note:
  1. Read TX/RX DL values from DL soft registers 0xE2 and 0xE3 respectively and calculate TX/RX latency based on Deterministic Latency Measurement for Triple-Speed Ethernet.
  2. Convert the TX and RX latency to 16 bits nanosecond and 16 bits fractional nanosecond format by multiplying them by 216 or 65536.
  3. Program the calculated 16 bits values to Triple-Speed Ethernet register.
    1. Program lower 16 bits TX latency values to TSE MAC register 0xD1, which is the TX fns value.
    2. Program upper 16 bits TX latency values to TSE MAC register 0xD2, which is the TX ns value.
    3. Program lower 16 bits RX latency values to TSE MAC register 0xD4, which is the RX fns value.
    4. Program upper 16 bits RX latency values to TSE MAC register 0xD5, which is the RX ns value.

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