Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.10.5. Intel LVDS Transmitter and Receiver Soft-CDR I/O Signals

These signals apply only to Intel® Agilex™ devices.
Table 96.  SERDES Control Signal
Name I/O Description
refclk I 125 MHz local reference clock oscillator.
txp O Positive signal for the transmitter serial data.
txn O Negative signal for the transmitter serial data.
rxp I Positive signal for the receiver serial data.
rxn I Negative signal for the receiver serial data.
rx_recovclkout O Recovered clock from LVDS receiver core.
lvds_tx_pll_locked O PLL locked indicator from LVDS transmitter core.

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