Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.8.4. Deterministic Latency Interface Signals

Table 89.  Deterministic Latency Interface Signals
Name I/O Width Description
o_sl_latency_sclk O 1

This signal is mapped to latency_sclk of E-tile Native PHY IP. Clock signal for latency measurement of the deterministic latency (DL) application.

The TX and RX asynchronous pulse is output from this signal in the DL module.

This signal is wired to TX and RX asynchronous pulse path in the Native PHY, and is used to determine the round-trip delay of the asynchronous-pulse path. Dividing the round-trip delay by 2 gives the 1-way delay of the asynchronous pulse.

o_sl_tx_rx_dl_measure_sel O 1 Multiplexer select signal for the transmitter and receiver latency measurement. This signal is mapped to both tx_dl_measure_sel and rx_dl_measure_sel of E-tile Native PHY IP.
  • 1 is for the datapath latency.
  • 0 is for the wire delay.
i_sl_tx_dl_async_pulse I 1 Asynchronous input pulse signal for the transmitter latency measurement of the deterministic latency application. This signal is mapped to tx_dl_async_pulse of E-tile Native PHY IP.
i_sl_rx_dl_async_pulse I 1 Asynchronous input pulse signal for the receiver latency measurement of the deterministic latency application. This signal is mapped to rx_dl_async_pulse of E-tile Native PHY IP.

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