Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
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1.8. Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet Intel® FPGA IP are obtained by compiling the Triple-Speed Ethernet Intel® FPGA IP using the Intel® Quartus® Prime software targeting a given device. The fMAX of all configurations is more than 125 MHz.
Table 5.  Resource Utilization for Triple-Speed Ethernet for Intel® Agilex™ DevicesThe following estimates are obtained by targeting the Intel® Agilex™ (AGFB014R24A3E3VR0) device.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

2048x32 4051 5634 21
2048x8 3865 5442 16
10/100 Mbps Small MAC

MII.

Full- and half-duplex only.

2048x32 1445 2120 11
1000 Mbps Small MAC

GMII.

Full-duplex only.

2048x32 1178 1937 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

N/A 898 1448 0

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

N/A 967 1638 1
1000BASE-X/SGMII 2XTBI PCS only

SGMII bridge enabled.

N/A 1329 2003 2

1000BASE-X.

N/A 1267 1917 2
10/100/1000 Mb Ethernet MAC with 1000BASEX/SGMII 2XTBI PCS

All MAC options enabled.

SGMII bridge enabled.

PMA block (GXB).

2048x32 5415 7882 22

All MAC options enabled.

SGMII bridge enabled.

PMA block (FGT).

2048x32 5213 7279 21
Table 6.  Resource Utilization for Triple-Speed Ethernet in Intel® Stratix® 10 DevicesThe following estimates are obtained by targeting the Intel® Stratix® 10 device as indicated below.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

Intel® Stratix® 10 (1SG280HN3F43E3VG) Device with Speed Grade -3
10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

2048x32 4055 5398 21
2048x8 3831 5139 16
10/100 Mbps Small MAC

MII.

Full- and half-duplex only.

2048x32 1460 2078 11
1000 Mbps Small MAC

GMII.

Full-duplex only.

2048x32 1158 1838 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

N/A 901 1333 0

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

N/A 945 1500 0
Intel® Stratix® 10 (1ST280EY3F55E3VG) Device with Speed Grade -3
1000BASE-X/SGMII 2XTBI PCS only SGMII bridge enabled. N/A 1306 1609 2
1000BASE-X N/A 1246 1543 2
10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS

All MAC options enabled.

SGMII bridge enabled.

PMA block (GXB).

2048x32 5292 7244 22
Table 7.  Resource Utilization for Triple-Speed Ethernet for Intel® Arria® 10 DevicesThe following estimates are obtained by targeting the Intel® Arria® 10 GX (10AX115R4F40I3SG) device with speed grade -3.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

2048x32 3817 5316 22
2048x8 3646 5142 17
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

2048x32 1354 1986 12
1000 Mbps Small MAC

GMII.

Full-duplex only.

2048x32 1079 1769 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

N/A 841 1162 2

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 662 995 2

1000BASE-X.

N/A 641 800 0
Table 8.  Resource Utilization for Triple-Speed Ethernet for Intel® Cyclone® 10 GX DevicesThe following estimates are obtained by targeting the Intel® Cyclone® 10 GX (10CX220YU484I6G) device with speed grade -6.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M20K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

2048x32 3819 5346 22
2048x8 3646 5185 17
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

2048x32 1358 1992 12
1000 Mbps Small MAC

GMII.

Full-duplex only.

2048x32 1083 1761 10
1000BASE-X/SGMII PCS

SGMII bridge enabled.

N/A 841 1175 2

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 662 992 2

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

N/A 877 1285 2
Table 9.  Resource Utilization for Triple-Speed Ethernet for Intel® Cyclone® 10 LP DevicesThe following estimates are obtained by targeting the Intel® Cyclone® 10 LP (10CL120YF780I7G) device.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M9K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

All MAC options enabled.

Full- and half-duplex.

2048x8 6724 4840 17
N/A 5863 4204 8
1000BASE-X/SGMII PCS

1000BASE-X.

SGMII bridge enabled.

N/A 1628 1133 2
10/100 Mbps Small MAC

MII.

Full and half-duplex only.

N/A 2416 1933 24
1000 Mbps Small MAC

GMII.

Full-duplex only.

N/A 1998 1645 24
Table 10.  Resource Utilization for Triple-Speed Ethernet for Intel® MAX® 10 DevicesThe following estimates are obtained by targeting the Intel® MAX® 10 (10M08DAF484C8G) device with speed grade -8.
IP Variation Settings FIFO Buffer Size (Bits) Logic Elements Logic Registers Memory

(M9K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

2048x32 6806 4943 30
2048x8 6593 4767 17
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

2048x32 2650 2117 24
1000 Mbps Small MAC

RGMII

Full-duplex only.

2048x32 2286 1862 24
Table 11.  Resource Utilization for Triple-Speed Ethernet for Stratix® V Devices The following estimates are obtained by targeting the Stratix® V GX (5SGXMA7N3F45C3) device with speed grade -3.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory 


(M20K Blocks/ MLAB Bits)

10/100 Mbps Small MAC

MII.

Full- and half-duplex.

2048x32 1261 2018 11/0

MII.

All MAC options enabled.

2048x32 1261 2018 11/0
1000 Mbps Small MAC

GMII.

All MAC options enabled.

2048x32 1227 1959 10/128

RGMII.

All MAC options enabled.

2048x32 1237 1984 10/128
10/100/1000 Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

N/A 3137 4298 5/2048
2048x8 3627 4971 10/2048
2048x32 3777 5145 16/2048

MII/GMII.

All MAC options enabled.

2048x32 3454 4928 16/768

RGMII.

All MAC options enabled.

2048x32 3466 4933 16/768
1000BASE-X/SGMII PCS 1000BASE-X. N/A 614 786 0/0

1000BASE-X.

SGMII bridge enabled.

N/A 839 1160 0/480

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

N/A 857 1250 0/480

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 2203 1991 5/2208

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

The reconfig controller is compiled with this variation.

N/A 1441 903 4/2048
10/100/1000 Mbps Ethernet MAC and 1000BASE-X/SGMII PCS

All MAC options enabled.

SGMII bridge enabled.

2048×32 4306 6132 16/1248

Default MAC options.

SGMII bridge enabled.

IEEE 1588v2 feature enabled.

0 5062 5318 4/1536
Table 12.  Resource Utilization for Triple-Speed Ethernet for Cyclone® V DevicesThe following estimates are obtained by targeting the Cyclone® V GX (5CGXFC7C7F23C8) device with speed grade -8.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M10K)

10/100/1000 Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

2048x32 1425 2299 21
2048x8 1387 2200 9
10/100 Mbps Small MAC

MII.

Full- and half-duplex.

2048x32 1338 2037 21
1000 Mbps Small MAC

RGMII.

Full-duplex only.

1

2048x32 1120 1829 20
1000BASE-X/SGMII PCS

1000BASE-X.

N/A 633 846 0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 783 1142 2

1000BASE-X.

SGMII bridge enabled.

N/A 850 1248 2
Table 13.  Resource Utilization for Triple-Speed Ethernet for Stratix® IV DevicesThe following estimates are obtained by targeting the Stratix® IV GX (EP4SGX530NF45C4) device with speed grade -4.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory 


(M9K Blocks/ M144K Blocks/MLAB Bits)

10/100 Mbps Small MAC

MII.

Full- and half-duplex.

2048x32 1410 2127 12/1/1408

MII.

All MAC options enabled.

2048x32 1157 1894 12/1/128
1000 Mbps Small MAC

GMII.

All MAC options enabled.

2048x32 1160 1827 12/1/176

RGMII.

All MAC options enabled.

2048x32 1170 1861 12/1/176
10/100/1000-Mbps Ethernet MAC

MII/GMII.

Full- and half-duplex.

N/A 2721 3395 0/0/3364
2048x8 3201 3977 8/0/3620
2048x32 3345 4425 12/1/3364

MII/GMII.

All MAC options enabled.

2048x32 3125 3994 12/1/2084

RGMII.

All MAC options enabled.

2048x32 3133 4021 12/1/2084
1000BASE-X/SGMII PCS 1000BASE-X. N/A 624 661 0/0/0

1000BASE-X.

SGMII bridge enabled.

N/A 808 986 2/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (LVDS_IO).

N/A 819 1057 2/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 1189 1212 1/0/160
10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS

All MAC options enabled.

SGMII bridge enabled.

2048×32 3971 4950 14/1/2084
Table 14.  Resource Utilization for Triple-Speed Ethernet for Cyclone® IV GX DevicesThe following estimates are obtained by targeting the Cyclone® IV GX (EP4CGX150DF27C7) device with speed grade -7.
IP Variation Settings FIFO Buffer Size (Bits) Logic Elements Logic Registers Memory

(M9K Blocks/ M144K Blocks/ MLAB Bits)

1000 Mbps Small MAC

RGMII

Full-duplex only.

2048x32 2161 1699 24/0/0
10/100/1000 Mbps Ethernet MAC

MII/GMII

Full- and half-duplex.

2048x32 5614 3666 31/0/0
1000BASE-X/SGMII PCS 1000BASE-X. N/A 1149 661 0/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 2001 1127 2/0/0
Table 15.  Resource Utilization for Triple-Speed Ethernet for Arria® II GX DevicesThe following estimates are obtained by targeting the Arria® II GX (EP2AGX260EF29I3) device with speed grade -3.
IP Variation Settings FIFO Buffer Size (Bits) Combinational ALUTs Logic Registers Memory

(M9K Blocks/ M144K Blocks/MLAB Bits)

10/100/1000 Mbps Ethernet MAC

RGMII.

All MAC options enabled.

Full- and half-duplex.

2048x32 3357 3947 26/0/1828
1000BASE-X/SGMII PCS 1000BASE-X. N/A 624 661 0/0/0

1000BASE-X.

SGMII bridge enabled.

PMA block (GXB).

N/A 1191 1214 1/0/160
1 This variant is targeting devices with –6 speed grade.

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