Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.8.1. Deterministic Latency Clock Signals

Table 86.  Deterministic Latency Clock Signals
Name I/O Width Description
i_dl_sampling_clk I 1 Sampling clock for deterministic latency logic. The default frequency value is 228.571429 MHz.

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