Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

6.1.8.2. Deterministic Latency Datapath Signals

Table 87.  Deterministic Latency Clock Signals
Name I/O Width Description
o_sl_tx_pma O 80 TX data to E-tile Native PHY (PMA side). Connect this signal to tx_parallel_data of E-tile Native PHY.
i_sl_rx_pma I 80 RX data from E-tile Native PHY (PMA side). Connect this signal to rx_parallel_data of E-tile Native PHY.

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