Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 683402
Date 5/30/2022
Public
Document Table of Contents

5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38)

The following table describes the read-only registers that collect the statistics on the transmit and receive datapaths. A hardware reset clears these registers; a software reset also clears these registers except aMacID. The statistics counters roll up when the counter is full.

The register description uses the following definitions:

  • Good frame—error-free frames with valid frame length.
  • Error frame—frames that contain errors or whose length is invalid.
  • Invalid frame—frames that are not addressed to the MAC function. The MAC function drops this frame.
Table 40.  Statistics Counters
Dword

Offset

Name R/W Description
0x18 – 0x19 aMacID RO The MAC address. This register is wired to the primary MAC address in the mac_0 and mac_1 registers.
0x1A aFramesTransmittedOK RO The number of frames that are successfully transmitted including the pause frames.
0x1B aFramesReceivedOK RO The number of frames that are successfully received including the pause frames.
0x1C aFrameCheckSequenceErrors RO The number of receive frames with CRC error.
0x1D aAlignmentErrors RO The number of receive frames with alignment error.
0x1E aOctetsTransmittedOK RO The number of data and padding octets that are successfully transmitted.

This register contains the lower 32 bits of the aOctetsTransmittedOK counter. The upper 32 bits of this statistics counter reside at the dword offset 0x0F.

0x1F aOctetsReceivedOK RO The number of data and padding octets that are successfully received, including pause frames.

The lower 32 bits of the aOctetsReceivedOK counter. The upper 32 bits of this statistics counter reside at the dword offset 0x3D.

0x20 aTxPAUSEMACCtrlFrames RO The number of pause frames transmitted.
0x21 aRxPAUSEMACCtrlFrames RO The number received pause frames received.
0x22 ifInErrors RO The number of errored frames received.
0x23 ifOutErrors RO The number of transmit frames with one the following errors:
  • FIFO overflow error
  • FIFO underflow error
  • Frames that encounter late or excessive collision occasions
  • Errors defined by the user application
0x24 ifInUcastPkts RO The number of valid unicast frames received.
0x25 ifInMulticastPkts RO The number of valid multicast frames received. The count does not include pause frames.
0x26 ifInBroadcastPkts RO The number of valid broadcast frames received.
0x27 Reserved Unused.
0x28 ifOutUcastPkts RO The number of valid unicast and erroneous frames transmitted, as well as unicast frames transmitted during late and excessive collision occasions.
0x29 ifOutMulticastPkts RO The number of valid multicast frames transmitted, as well as multicast frames transmitted during late and excessive collision occasions, excluding pause frames.
0x2A ifOutBroadcastPkts RO The number of valid and erroneous broadcast frames transmitted, as well as broadcast frames transmitted during late and excessive collision occasions.
0x2B etherStatsDropEvents RO The number of frames that are dropped due to MAC internal errors when FIFO buffer overflow persists.
0x2C etherStatsOctets RO The total number of octets received. This count includes both good and errored frames.

This register is the lower 32 bits of etherStatsOctets. The upper 32 bits of this statistics counter reside at the dword offset 0x3E.

0x2D etherStatsPkts RO The total number of good and errored frames received.
0x2E etherStatsUndersizePkts RO The number of frames received with length less than 64 bytes, including pause frames. This count does not include errored frames.
0x2F etherStatsOversizePkts RO The number of frames received that are longer than the value configured in the frm_length register. This count does not include errored frames.
0x30 etherStatsPkts64Octets RO The number of 64-byte frames received. This count includes good and errored frames.
0x31 etherStatsPkts65to127Octets RO The number of received good and errored frames between the length of 65 and 127 bytes.
0x32 etherStatsPkts128to255Octets RO The number of received good and errored frames between the length of 128 and 255 bytes.
0x33 etherStatsPkts256to511Octets RO The number of received good and errored frames between the length of 256 and 511 bytes.
0x34 etherStatsPkts512to1023Octets RO The number of received good and errored frames between the length of 512 and 1023 bytes.
0x35 etherStatsPkts1024to1518Octets RO The number of received good and errored frames between the length of 1024 and 1518 bytes.
0x36 etherStatsPkts1519toXOctets RO The number of received good and errored frames between the length of 1519 and the maximum frame length configured in the frm_length register.
0x37 etherStatsJabbers RO Too long frames with CRC error.
0x38 etherStatsFragments RO Too short frames with CRC error.
0x39 Reserved Unused.
Extended Statistics Counters (0x3C – 0x3E)
0x3C msb_aOctetsTransmittedOK RO Upper 32 bits of the respective statistics counters. By default all statistics counters are 32 bits wide. These statistics counters can be extended to 64 bits by turning on the Enable 64-bit byte counters parameter.

To read the counter, read the lower 32 bits first, then followed by the extended statistic counter bits.

0x3D msb_aOctetsReceivedOK RO
0x3E msb_etherStatsOctets RO

Did you find the information on this page useful?

Characters remaining:

Feedback Message