Triple-Speed Ethernet Intel® FPGA IP User Guide

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ID 683402
Date 5/30/2022
Public
Document Table of Contents

1. About This IP

Updated for:
Intel® Quartus® Prime Design Suite 22.1
IP Version 20.0.0
The Triple-Speed Ethernet Intel® FPGA IP is a configurable intellectual property (IP) core that complies with the IEEE 802.3 standard.

It incorporates a 10/100/1000 Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded physical medium attachment (PMA) built with either on-chip transceiver I/Os or LVDS I/Os. When offered in MAC-only mode, the IP connects with an external PHY chip using Media Independent Interface (MII), Gigabit Media Independent Interface (GMII), or Reduced Gigabit Media Independent Interface (RGMII). The IP was tested and successfully validated by the University of New Hampshire InterOperability Lab.

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